Sundance SMT329 - Manual (Page 24)

3C-3D Virtex4 code revision
3E-3F Manufacturer ID
4.4.1.1 VME Board ID Register (address 00-01)
The bit definitions for this register are:
15–12 11–0
ID1 ID2
R, 0101 R, 0000 0111 1011
Always reads as 507B hex.
4.4.1.2 VME Device Type Register (address 02-03)
The bit definitions for this register are:
15–12 11–0
Memory Size 8 Model Code 329
R, 1000 R, 0001 0100 1001
Memory size is defined as the number of significant bits in an A32 address used to specify the
sram base address.
So this register reads as: 0x8149
4.4.1.3 VME Master Status and Control Register (address 04-05)
The bit definitions for the VME Master Status and Control register are:
15 14-4 3 2-1 0
A32 Enabled Ready Reset board
RW, 0 R,000 0000 0001 R, x R, 10 RW, 0
Bit 15 is cleared by a board reset so that the A32 base address registers can be initialised
before A32 enable is set. A32 enable MUST be set to allow A32 access to the rest of the board.
If this bit is clear (0) then no A32 access will be decoded and a bus error will
occur for all A32 read/write cycles.
It is very strongly recommended that all VME bus cycles have some form of BUS_ERROR
checking enabled, as it is an essential error reporting feature which should not be ignored.
User Manual SMT329 Page 24 of 52 Last Edited: 09/02/2007 10:58:00