Verilink DIU 2130 (880-503297-001) Product Manual - Manual (Page 36)

DIU 2130 Configuration
3-12 Verilink
If the value selected is other than ideal, the DIU 2130 may be
sampling the transmit data lead at or near the transition between
one bit and the next. This will cause errors because the DIU 2130
may sense what is actually a one as a zero or vice versa. Longer
cables and higher data rates cause more rounding of the otherwise
square transitions from one bit to the next. Poorer quality DTE
cables have higher capacitance per foot which accelerates the
rounding off effect on pulse edges. This means that even as the
width of a data bit is decreasing, the portion of that data bit that
may be used to reliably sample is also decreasing. Thus, the higher
the data rate the more critical this selection becomes.
For receive data and the relationship to receive clock, long cables
do not present problems of this sort. This is because both the
receive data and the receive clock originate in the DCE, travel the
same length of cable and are subjected to the same delay. They
arrive at the DTE still in phase with each other. Transmit data
presents a different case—the transmit clock signal is generated by
the DCE. It must travel the (unknown) length of cable to reach the
DTE being subject to (unknown) delay. The DTE does not react to
transitions of transmit clock until they reach it—some delay will
always be present. Once the DTE senses a clock transition it
presents the next data bit which is to be transmitted. This data
must now travel the length of cable in the opposite direction so
that it will arrive at the DCE before it samples again.
Some manufacturers, among them Cisco Systems, take the transmit
clock signal provided by the DCE and loop it back toward the DCE
on an optional third pair of clock leads. In V.35 this pair is SCTE
(Serial ClockTransmit External) plus and minus; in RS449 they are
called TT (Terminal Timing). This is the actual clock signal which
the DCE originally sent, so it is at the same frequency, but it is
subjected to the same delay and waveshape distortion as the
transmit data, since it travels the same length of cable.
When TT is selected the DIU 2130 looks to SCTE or TT for a clock
signal and uses that clock to control when it samples transmit data.
Since this clock is expected to be perfectly in phase with transmit
data it solves the sampling issues described above. Therefore
Verilink Tech Support recommends selecting this option whenever
the DTE presents this optional third clock signal.
If the DTE is not actually presenting a clock signal on the SCTE or
TT pair, selecting TT will cause a high error rate.
LOS Lead
If desired the DIU may be configured to monitor either one of two leads
(RTS or DTR) which typically are asserted by the DTE. When this lead
is not asserted an alarm is then reported. In this way the DIU can be
relied upon to report if one of these conditions occurs:
DTE is powered down
DTE cable is disconnected
DTE goes offline