Verilink DIU 2130 (880-503297-001) Product Manual - Manual (Page 89)

DIU/DIM Details
Verilink 7-9
appropriate DS0 channel time slots of the backplane DIU data bus
assigned to the CSU. In the figure, four channels are assigned to
each of the four DIU data ports for network transmission.
The composite data going to the CSU contains the multiplexed data
from all associated DIUs. Upon receiving this data, the CSU
multiplexes it into a DS1 signal for transmission over the T1
network. It also sends all-ones bytes on all unassigned channels.
In the other direction of transmission, the CSU routes the incoming
signal to all DIUs via the assigned data bus. Each DIU demultiplexes
the incoming signal to derive the individual channel data.
The CSU also sends clock and framing signals to the DIUs over the
assigned data bus. These signals synchronize the DIU transmit and
receive side circuits to the CSU. The CSU derives the CSU and DIU
transmit clocks and the DIU receive clock from one of the following
reference clocks:
• The internal crystal oscillator clock generated in the CSU
circuits.
• An external 1.544 MHz DS1/AMI
• optional with a TIU 2850 timing coprocessor, or
• RS-422 or TTL reference clock.
• External timing N × 56 or N × 64 kbit/s; optional through the
TIU 2850 timing coprocessor.
• The incoming signal from the network or equipment interfaces
(loop timing).
• Terminal Timing (TT) signal from a data terminal equipment
(DTE) device connected to a DIU 2130.
The CSU accommodates up to 24 DIU 2130s over the selected data
bus. It can also interface with any combination of DIUs whose
aggregate capacity is 24 DS0 channel time slots.