KEPCO TMA VXI-27 - Manual (Page 35)

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TMA VXI -27 101602
3.5.9.4 MULTIPLE LOGICAL INSTRUMENTS
The TMA VXI-27 is a SCPI device that supports multiple logical instruments; it allows a choice
between two methods of status reporting. The status reporting default upon powerup treats the
unit as a single channel instrument. When multiple channels are in use, a SCPI compliant status
structure can be selected which provides an INSTrument summary status register and an indi-
vidual instrument ISUMmary for each logical instrument. These registers are equivalent to the
Status Questionable register of a single channel instrument and are also found in the STATus
Questionable register for the selected channel. The contents of the STATus Questionable regis-
ter can also contain the summary of all instruments as shown in Figure 3-7.
The selection of the status reporting structure is controlled by the SYStem:SET SI (Instrument
Structure) command, either SI0 (off) or SI1 (on). The power-up default is the off condition. To
enable the SCPI compliant mode of operation for multiple logical instruments the user must
send SYSTem:SET SI1 to the TMA VXI-27 power supply during initialization. The SI1 state is
not remembered when the unit is turned off. To return to the standard method of reporting the
selected device’s status without turning the unit off, send SYSTem:SET SI0.
When the TMA VXI-27 power supply is set up for SCPI compliant status reporting for multiple
channels, the specific instrument’s Questionable register is found in the
STAT:QUES:INST:ISUM<n> register. This register has the same bit structure as the single
channel Questionable register. The ISUM enable register is ANDed with the bits of the chan-
nel’s ISUM register and its bit is placed in the INST register. The Questionable register bits are
the logical ORing of all channels’ Questionable ISUM register. This is shown in figure 3-7.
The ISUMmary registers set the INSTrument register, which in turn sets bit 13 of the QUEStion-
able or OPERation status register. This is shown pictorially in Figure 3-7.
The STATUS:QUESTIONABLE and STATUS:QUESTIONABLE:CONDITION registers are the
same in this mode of status reporting. The condition register indicates the status of the various
event registers and bits set are only cleared if the source of the bit is cleared.