Table c-4. questionable instrument register 0 bits, C.33 status:questionable:instrument1? query, Table c-5. questionable instrument register 1 bits – KEPCO TMA VXI-27 User Manual
Page 59: C.34 status:questionable:instrument2? query, Table c-6. questionable instrument register 2 bits, C.35 status:questionable:instrument:enable command, C.33, C.34, C.35, Questionable instrument register 0 bits
C-10
TMA VXI-27 101602
14 are cleared. Bit 0 which indcates the summary of the bits in Instrument Register 1 (inst1 register)
remains set until the inst1 register is read.
C.33 STATus:QUEStionable:INSTrument1? QUERY
STAT:QUES:INST1?
Syntax:
Short Form: STAT:QUES:INST1? Long Form: STATus:QUESionable:INSTrument1?
Return Value: <int_value> actual register value
Description: Reads Questionable Instrument Register 1 (see Table C-5). Unit returns value of Instrument Regis-
ter 1 (inst1 register). The bits of this register are set when at leat one bit in the specified channel’s
ISUM register was set previously and the specific enable bit was also set. When this register is read,
bits 1 - 14 are cleared. Bit 0 which indcates the summary of the bits in Instrument Register 2 (inst2 reg-
ister)
remains set until the inst2 register is read.
C.34 STATus:QUEStionable:INSTrument2? QUERY
STAT:QUES:INST2?
Syntax:
Short Form: STAT:QUES:INST2? Long Form: STATus:QUESionable:INSTrument2?
Return Value: <int_value> actual register value
Description: Reads Questionable Instrument Register 2 (see Table C-6). Unit returns value of Instrument Regis-
ter 2 (inst2 register). The bits of this register are set when at leat one bit in the specified channel’s
ISUM register was set previously and the specific enable bit was also set. When this register is read,
bits 1 - 14 are cleared.
STAT:QUES:INST:ENAB
C.35 STATus:QUEStionable:INSTrument:ENABle COMMAND
Syntax:
Short Form: STAT:QUES:INST:ENAB <int_value>
Long Form: STATus:QUESionable:INSTrument:ENABle <int_value>
Description: Programs Questionable Instrument Register 0 Enable Register (see Table C-3). The Question-
able Instrument Register 0 Enable Register is a mask which determines which channels are allowed
to set Questionable Instrument Register 0.
TABLE C-4. QUESTIONABLE INSTRUMENT REGISTER 0 BITS
CONDITION
NU
CH
14
CH
13
CH
12
CH
11
CH
10
CH
9
CH
8
CH
7
CH
6
CH
5
CH
4
CH
3
CH
2
CH
1
INST1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VALUE
32768 16384
8192 4096 2048
1024
512
256
128
64
32
16
8
4
2
1
CH
CHANNEL
NU
NOT USED
INST1 INSTRUMENT REGISTER 1
TABLE C-5. QUESTIONABLE INSTRUMENT REGISTER 1 BITS
CONDITION
NU
CH
28
CH
27
CH
26
CH
25
CH
24
CH
23
CH
22
CH
21
CH
20
CH
19
CH
18
CH
17
CH
16
CH
15
INST2
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VALUE
32768 16384
8192 4096 2048
1024
512
256
128
64
32
16
8
4
2
1
CH
CHANNEL
NU
NOT USED
INST1 INSTRUMENT REGISTER 1
TABLE C-6. QUESTIONABLE INSTRUMENT REGISTER 2 BITS
CONDITION
NU
CH
31
CH
30
CH
29
NU
BIT
15-4
3
2
1
0
VALUE
32768-16
8
4
2
1
CH
CHANNEL
NU
NOT USED