FUJITSU MCM3064AP User Manual
Page 110
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Host Interface
4-40
C156-E227-01EN
When the FR register is 95h, the ODD responds as follows at the end of the
command:
-
The CL register responds with 00h.
-
The CH register responds with the following values.
Table 4.34 Cylinder High register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
POWER_EJ
LOCK
PRV_ENAB
POWER_EJ: Sets 1.
LOCK: Sets 1.
PRV_ENAB: Sets 1 when the media status notification function is enabled.
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