5 system core logic, Hardware functional overview – FIC M296 User Manual

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Hardware Functional Overview

reduce the number of instructions required to execute a particular program task providing
overall performance increase

• Rapid Execution Engine

- Arithmetic Logic Units (ALUs) run at twice core frequency for faster processing of
certain instructions for higher execution throughput and less wait time

• Enhanced Intel® SpeedStep™ Technology

- Real-time dynamic switching of voltage and frequency between maximum performance
and battery-optimized operation, based on CPU demand, for longer battery life

• 0.13 Micron Process Technology

- Smallest, fastest, transistors enable higher speeds, lower power consumption in small
mobile package

• Thin & Small Package Technology (Micro FCPGA chip packaging)

- Intel packaging technology requires less space, for higher performance in thinner,
lighter systems

4.5 System Core Logic

The system core logic function of the notebook is implemented on the CPU module and
motherboard using the SiS645DX IGUI HMAC.

The SiS645DX Host & Memory & AGP

Controller integrates a high performance host interface for Intel Pentium 4 processor, a high
performance memory controller, a AGP interface, and SiS MuTIOL Technology connecting w/
SiS962L MuTIOL Media IO.

The SiS645DX Host Interface features the AGTL & AGTL+ compliant bus driver
technology with integrated on-die termination to support Intel Pentium 4 series processors
with FSB 100 MHz and over clocking up to 133MHz. It provides a 12-level In-Order-Queue
to support maximum outstanding transactions on host bus up to 12. The host interface plays
the role of processor transactions’

dispatcher. It dispatches transactions to Memory, I/O

interface and AGP bus. Transactions to different destinations can be dispatched concurrently
in order to maximum pipeline efficiency. In addition to dispatching processor’s transactions to
corresponding destinations, host interface also forward DMA transactions from AGP masters
and I/O masters to host bus for snooping, including master interrupt delivery. The memory
controller can support both DDR and SDR. It can offer bandwidth up to 2.7GB/s under
DDR333 and 1GB/s under PC133 in order to sustain the bandwidth demand from host
processor, as well as the multi I/O masters and AGP masters. The Memory Controller mainly
comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface.
The Memory Arbiter arbitrates a plenty of memory access Host Controller, and I/O bus
masters based on a default optimized priority list with the capability of dynamically prioritizing
the I/O bus master requests in a bid to offering privileged service to 1) the isochronous
downstream transfer to guarantee the min. latency & timely delivery,or 2) the PCI master
upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the
memory access requests pushed into the M-data queue, any command compliant to the
paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD
Queues further orders and forwards these queuing requests to the Memory Interface in an
effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in
the background when the data requests streamlines in the foreground. The memory
controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in
ACPI S3 state in which only AUX source deliver power.
The AGP interface can support external AGP slot with AGP 1X/2X/4X capability and Fast
Write Transactions. A high bandwidth and mature SiS MuTIOL technology is incorporated to
connect SiS645DX and SiS962L MuTIOL Media I/O together. SiS MuTIOL technology is
developed into three layers, the Multi-threaded I/O Link Channels Layer delivering 1.2GB
bandwidth to connect embedded DMA Master devices and external PCI masters to interface
to Multi-threaded I/O Link Packet layer, the Multi-threaded I/O Link Packet Layer in SiS961
to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link Channels layer
to/from SiS645DX, and the Multi threaded I/O Link Packet Layer in SiS645DX to transfer


FIC M295 / M296 Service Manual

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