FIC M296 - Manual (Page 107)

Hardware Functional Overview
integrated power management module incorporates the ACPI 1.0b compliance functions, the
APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1.
Numerous power-up events and power down events are also supported. 24 general purposed
I/O pins are provided to give an easy to use logic for specific application. In addition, the
SiS962L supports Deeper Sleep power state for Intel Mobile processor. For AMD processor,
the SiS962L use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.
A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS645DX
and SiS962L MuTIOL Media I/O together. SiS MuTIOL technology is developed into three
layers, the Multi-threaded I/O Channels Layer delivering 1.2GB bandwidth to connect
embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O
Channels layer, the Multi-threaded I/O Packet Layer in SiS962L to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Channels layer to/from SiS645DX, and the Multi-
threaded I/O Packet Layer in SiS645DX to transfer data w/ 533 MB/s from/to memory sub-
system to/from the Multi-threaded I/O Packet Layer in SiS962L.
The SiS 962L MuTIOL Media I/O functions and capabilities include:
High performance SiS MuTIOL Technology Interconnecting SiS North bridge and
South bridge chips
• Bi-directional 16-bit data bus
• 533MB/s performance in 4x66 MHz mode
• Distributed Arbitration Scheme
• Supports Back to Back Transaction
Integrated Multi-threaded I/O link ensures concurrency of upstream/down stream data
transfer
with 1.2GB/s bandwidth
Multiple DMA Bus Architecture
• Concurrent Servicing of all DMA Devices: Dual IDE Controllers, Dual USB HCs, MAC
Controller, and Audio/Modem DMA Controller
• Separate 32 Bit Input and Output Data Bus Scheme for each DMA Device
• Advanced Performance Merits of Split & Pipelined Transaction and Concurrent
• Execution among Multi-I/O Devices
Integrated MuTIOL Connect to PCI Bridge
• PCI 2.2 Specification Compliance
• Supports up to 6 PCI Masters
• Two Prefetch cache Buffers support 2 delayed transactions
• Fairness Rotating PCI Arbiter Scheme with Option to Place PCI Master 0 as the Highest
Priority
• Write Promotion Mechanism to Guarantee the 10 µs Time Limit of PCI Memory Write
Dual IDE Master/Slave Controller
• Integrated Multithreaded I/O Link Mastering with Read Pipelined Streaming
• Dual Independent IDE Channels Each with 32 DW FIFO
• Native and Compatibility Mode
• PIO Mode 0, 1, 2, 3, 4 and Multiword DMA Mode 0, 1, 2
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FIC M295 / M296 Service Manual