Motorola TMS320C6711D User Manual
Motorola Hardware
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Table of contents
Document Outline
- SPRS292A - TMS320C6711D
- features
- Table of Contents
- REVISION HISTORY
- GDP and ZDP BGA packages (bottom view)
- description
- device characteristics
- device compatibility
- functional block and CPU (DSP core) diagram
- CPU (DSP core) description
- memory map summary
- peripheral register descriptions
- signal groups description
- DEVICE CONFIGURATIONS
- TERMINAL FUNCTIONS
- development support
- device support
- CPU CSR register description
- cache configuration (CCFG) register description
- interrupt sources and interrupt selector
- EDMA module and EDMA selector
- PLL and PLL controller
- general-purpose input/output (GPIO)
- power-down mode logic
- power-supply sequencing
- power-supply decoupling
- IEEE 1149.1 JTAG compatibility statement
- EMIF device speed
- EMIF big endian mode correctness
- bootmode
- reset
- absolute maximum ratings over operating case temperature range (unless otherwise noted)†
- recommended operating conditions‡
- electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)
- PARAMETER MEASUREMENT INFORMATION
- INPUT AND OUTPUT CLOCKS
- timing requirements for CLKIN†‡§ (see Figure 22)
- timing requirements for CLKIN†‡§ (see Figure 22)
- switching characteristics over recommended operating conditions for CLKOUT2†‡ ( see Figure 23)
- switching characteristics over recommended operating conditions for CLKOUT3†§ (see Figure 24)
- timing requirements for ECLKIN† (see Figure 25)
- switching characteristics over recommended operating conditions for ECLKOUTद (see Figure 26)
- ASYNCHRONOUS MEMORY TIMING
- SYNCHRONOUS-BURST MEMORY TIMING
- SYNCHRONOUS DRAM TIMING
- HOLD\/HOLDA\ TIMING
- BUSREQ TIMING
- RESET TIMING
- EXTERNAL INTERRUPT TIMING
- HOST-PORT INTERFACE TIMING
- MULTICHANNEL BUFFERED SERIAL PORT TIMING
- timing requirements for McBSP†‡ (see Figure 46)
- switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 46)
- timing requirements for FSR when GSYNC = 1 (see Figure 47)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 48)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 48)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 49)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 49)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 50)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 50)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 51)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 51)
- TIMER TIMING
- GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
- JTAG TEST-PORT TIMING
- MECHANICAL DATA