Intel GD82559ER - Manual (Page 28)

GD82559ER — Networking Silicon
22 Datasheet
• This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance.
• This feature should be used only when the CLS register in PCI Configuration space is set to 8
or 16 Dwords.
• The 82559ER reads all control data structures (including Receive Buffer Descriptors) from the
first Dword (even if it is not required) to maintain cache line alignment.
4.2.1.2.3 Error Handling
Data Parity Errors: As an initiator, the 82559ER checks and detects data parity errors that occur
during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register,
bit 6), the 82559ER also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration
Status register, bit 8). In addition, if the error was detected by the 82559ER during read cycles, it
sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
4.2.2 Clockrun Signal
The CLKRUN# signal is used to control the PCI clock as defined in the PCI Mobile design guide
and is compliant with the PCI Mobile design guide. The Clockrun signal is an open drain I/O
signal. It is used as a bidirectional channel between the host and the devices.
• The host de-asserts the CLKRUN# signal to indicate that the PCI clock is about to be stopped
or slowed down to a non-operational frequency.
• The host asserts the CLKRUN# signal when the interface clock is either running at a normal
operating frequency or about to be started.
• The 82559ER asserts the CLKRUN# signal to indicate that it needs the PCI clock to prevent
the host from stopping the PCI clock or to request that the host restore the clock if it was
previously stopped.
Proper operation requires that the system latency from the nominal PCI CLK to CLKRUN#
assertion should be less than 0.5
µ
s. If the system latency is longer than 0.5
µ
s, the occurrence of
receive overruns increases. For use in these types of systems, the Clockrun functionality should be
disabled (see
Section 8.1.12, “General Control Register” on page 61 ). In this case, the 82559ER
will claim the PCI clock even during idle time. If the CLKRUN# signal is not used, it should be
connected to a pull-down resistor (62K
Ω)
. The value of the resistor selected is dependent on the
ND-TREE set-up used (i.e. the test fixture must be able to overdrive pull-down).
4.2.3 Power Management Event Signal
The 82559ER supports power management indications in the PCI mode. The PME# output pin
provides an indication of a power management event to the system. PCI Power Management
In addition to the base functionality of the 82558 B-step, the 82559 family supports a larger set of
wake-up packets and the capability to wake the system on a link status change from a low power
state. The 82559ER enables the host system to be in a sleep state and remain virtually connected to
the network. After a power management event or link status change is detected, the 82559ER will
wake the host system. The sections below describe these events, the 82559ER power states, and
estimated power consumption at each power state.