Intel GD82559ER - Manual (Page 74)

GD82559ER — Networking Silicon
68 Datasheet
9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions
9.2 MDI Registers 8 - 15
Registers eight through fifteen are reserved for IEEE.
9.3 MDI Register 16 - 31
9.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions
Bit(s) Name Description Default R/W
15:5 Reserved These bits are reserved and should be set to 0b. 0 RO
4 Parallel Detection
Fault 1 = Fault detected via parallel detection (multiple link
fault occurred)
0 = No fault detected via parallel detection
This bit will self-clear on read
0 RO
SC
LH
3 Link Partner Next
page Able 1 = Link Partner is Next Page able
0 = Link Partner is not Next Page able
0 RO
2 Next Page Able 1 = Local drive is Next Page able
0 = Local drive is not Next Page able
0 RO
1 Page Received 1 = New Page received
0 = New Page not received
This bit will self-clear on read.
0 RO
SC
LH
0 Link Partner Auto-
Negotiation Able 1 = Link Partner is Auto-Negotiation able
0 = Link Partner is not Auto-Negotiation able
0 RO
Bit(s) Name Description Default R/W
15:14 Reserved These bits are reserved and should be set to 00b 00 RW
13 Carrier Sense
Disconnect
Control This bit enables the disconnect function.
1 = Disconnect function enabled
0 = Disconnect function disabled
0 RW
12 Transmit Flow
Control Disable This bit enables Transmit Flow Control
1 = Transmit Flow Control enabled
0 = Transmit Flow Control disabled
0 RW
11 Receive De-
Serializer In-Sync
Indication This bit indicates status of the 100BASE-TX Receive
De-Serializer In-Sync. -- RO
10 100BASE-TX
Power-Down This bit indicates the power state of 100BASE-TX
PHY unit.
1 = Power-Down
0 = Normal operation
1 RO
9 10BASE-T
Power-Down This bit indicates the power state of 100BASE-TX
PHY unit.
1 = Power-Down
0 = Normal operation
1 RO