Jameco Electronics Rabbit 3000 - Manual (Page 133)

124 Rabbit 3000 Microprocessor
8.7 Instruction and Data Space Support
Instruction and Data space (I and D space) support is accomplished by optionally invert-
ing address lines A16 and/or A19 when the processor accesses D space, but not inverting
those lines when the processor accesses I space. The MMIDR register (see Table 8-8) is
used to control this inversion. It is important to understand that the bit inversion of A16
and A19 associated with I and D space occurs before the upper 2 bits of the 20-bit address
are used to determine the quadrant and thus the bank register that is going to control mem-
ory access. This contrasts with the optional address bit inversion of A19 and A18 con-
trolled by the 4 memory bank control registers (see Table 8-3) that takes place after the
quadrant has been computed.
To make this clear, let’s look at an example. Suppose a 1 megabyte flash memory is con-
trolled by /CS0, /WE0, and /OE0. Suppose this memory is accessed as part of the first
quadrant and MB0CR is set up to enable /CS0 and /WE0 or /OE0 on accesses to this bank.
Then if A18 and A19 are zero, the first 256K of the flash memory will be visible in the
first 256K of the physical memory. If access is made to the second quadrant, the memory
will not be selected unless MB1CR is mapped to the flash memory. However, if A18 is
inverted by setting bit 4 in MB0CR to a 1, then the second 256K of the flash will be
mapped into the first quadrant. A18 will have been inverted, but he quadrant does not
change because this inversion occurs after the quadrant has been selected.
The inversion of A19 or A16 controlled by the MMIDR register on D space accesses is
used to separate I and D space to different memory locations. The separation of I and D
space can only occur for the first two memory zones in the64K space. For each zone, the
root code segment and the data segment either or both of A19 and A16 can be inverted.
The reasoning behind these choices is that a normal memory map places flash memory in
the lower 512K of the physical memory space. RAM memory begins at 512K. By invert-
ing A19 on D space accesses, memory mapped to the lower 512K and held in flash will be
switched to RAM for D accesses. By inverting A16, D accesses will be switched to an
adjacent 64K page, which would normally still be in the lower 512K memory or flash. To
see how this works consider that data are of two different types—constants stored in flash
memory and variables, which must be stored in RAM. Because there are two types of data,
it is desirable to divide the D space into two zones, one for constants and one for variables,
as shown in Figure 8-5. In a combined I and D space model the root code segment holds
both code and data constants in flash memory. The data segment holds data variables in
RAM. In the separate I and D space model, the root code segment and the data segment
Table 8-8. Use of MMIDR Register to Control Inversion of Address Lines A16 and A19
Bits 7:5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
000 1–force
/CS1
always
enabled 1–Invert A19 for
data accesses in data
segment before
quadrant selection 1–Invert A16 for
data accesses in
data segment 1–Invert A19 for
data accesses in root
segment before
quadrant selection 1–Invert A16 for
data accesses in
root segment.