Jameco Electronics Rabbit 3000 - Manual (Page 168)

User’s Manual 159
11.2.1 Using Timer B
Normally the prescaler is set to divide perclk/2 by a number that provides a counting rate
appropriate to the problem. For example, if the clock is 22.1184 MHz, then perclk/2 is
11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of the
10-bit clock in 92.6 µs.
Normally an interrupt will occur when either of the comparators in Timer B generates a
pulse. The interrupt routine must detect which comparator is responsible for the interrupt
and dispatch the interrupt to a service routine. The service routine sets up the next match
value, which will become the match value after the next interrupt. If the clocked parallel
ports are being used, then a value will normally be loaded into some bits of the parallel
port register. These bits will become the output bits on the next match pulse. (It is neces-
sary to keep a shadow register for the parallel port unless the bit-addressable feature of
Ports D and E is used.)
If you wish to read the time from the Timer B counter, either during an interrupt caused by
the match pulse or in some other interrupt routine asynchronous to the match pulse, you
will have to use a special procedure to read the counter because the upper 2 bits are in a
different register than the lower 8 bits. The following method is suggested.
1. Read the lower 8 bits (read TBCLR register).
2. Read the upper 2 bits (read TBCMR register)
3. Read the lower 8 bits again (read TBCLR register)
4. If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits, there
has been a carry to the upper 2 bits. In this case, read the upper 2 bits again and decre-
ment those 2 bits to get the correct upper 2 bits. Use the first read of the lower 8 bits.
This procedure assumes that the time between reads can be guaranteed to be less than 256
counts. This can be guaranteed in most systems by disabling the priority 1 interrupts,
which will normally be disabled in any case in an interrupt routine.
It is inadvisable to disable the high-priority interrupts (levels 2 and 3) as that defeats their
purpose.
If speed is critical, the three reads of the registers can be performed without testing for the
carry. The three register values can be saved and the carry test can be performed by a
lower priority analysis routine. Since the upper 2 bits are in the TBCMR register at
address 0x0BE, and the lower 8 bits are in TBCLR at address 0x0BF, both registers can be
read with a single 16-bit I/O instruction. The following sequence illustrates how the regis-
ters could be captured.
; enter from external interrupt on pulse input transition
; 19 clocks latency plus 10 clocks interrupt execution
push af ; 7
push hl
ioi ld a,(TBCLR) ; 11 get lower 8 bits of counter
ioi ld hl,(TBCMR) ;13 get l=upper, h=lower