Jameco Electronics Rabbit 3000 - Manual (Page 179)

170 Rabbit 3000 Microprocessor
Table 12-11. Status Register Asynchronous Mode Only (All Ports)
Serial Port x Status Register (SASR) (Address = 0xC3)
(SBSR) (Address = 0xD3)
(SCSR) (Address = 0xE3)
(SDSR) (Address = 0xF3)
(SESR) (Address = 0xCB)
(SFSR) (Address = 0xDB)
Bit(s) Value Description (Async mode only)
7
0 The receive data register is empty—no input character is ready.
1
There is a byte in the receive buffer. The transition from "0" to "1" sets the
receiver interrupt request flip-flop. The interrupt FF is cleared when the
character is read from the data buffer. The interrupt FF will be immediately set
again if there are more characters available in the FIFO or shift register to be
transferred into the data buffer.
6
0 The byte in the receive buffer is data, received with a valid Stop bit.
1
Address bit or 9th (8th) bit received. This bit is set if the character in the receiver
data register has a 9th (8th) bit. This bit is cleared and should be checked before
reading a data register since a new data value with a new address bit may be
loaded immediately when the data register is read.
The byte in the receive buffer is an address, or a byte with a framing error. If an
address bit is not expected. If the data in the buffer is all zeros, this may be a
Break.
5
0 The receive buffer was not overrun.
1
This bit is set if the receiver is overrun. This happens if the shift register and the data
register are full and a start bit is detected. This bit is cleared when the receiver data
register is read.
4 0 This bit is always zero in async mode.
3
0 The transmit buffer is empty.
1
T ransmitter data buffer full. This bit is set when the transmit data register is full,
that is, a byte is written to the serial port data register. It is cleared when a byte is
transferred to the transmitter shift register or FIFO, or a write operation is
performed to the serial port status register. This bit will request an interrupt on
the transition from 1 to 0 if interrupts are enabled. Transmit interrupts are cleared
when the transmit buffer is written, or any value (which will be ignored) is
written to this register.
2
0 The transmitter is idle.
1
Transmitter busy bit. This bit is set if the transmitter shift register is busy sending
data. It is set on the falling edge of the start bit, which is also the clock edge that
transfers data from the transmitter data register to the transmitter shift register.
The transmitter busy bit is cleared at the end of the stop bit of the character sent.
This bit will cause an interrupt to be latched when it goes from busy to not busy
status after the last character has been sent (there are no more data in the
transmitter data register).
1:0 00 These bits are always zero in async mode.