Jameco Electronics Rabbit 3000 - Manual (Page 32)

User’s Manual 23
3.2 Memory Mapping
Although the Rabbit memory mapping scheme is fairly complex, the user rarely needs to
worry about it because the details are handled by the Dynamic C development system.
Except for a handful of special instructions (see Section 19.5, “16-bit Load and Store 20-
bit Address”.), the Rabbit instructions directly address a 64K data memory space. This
means that the address fields in the instructions are 16 bits long and that the registers that
may be used as pointers to memory addresses (index registers (IX, IY), program counter
and stack pointer (
SP )) are also 16 bits long.
Because Rabbit instructions use 16-bit addresses, the instructions are shorter and can exe-
cute much faster than if, for example, 32-bit addresses were used. The executable code is
very compact.
The Rabbit memory-mapping unit is similar to, but more powerful than, the Z180 mem-
ory-mapping unit. Figure 3-2 illustrates the relationship among the major components
related to addressing memory.
Figure 3-2. Addressing Memory Components
The memory-mapping unit receives 16-bit addresses as input and outputs 20-bit addresses.
The processor (except for certain
LDP instructions) sees only a 16-bit address space. That
is, it sees 65536 distinctly addressable bytes that its instructions can manipulate. Three
segment registers are used to map this 16-bit space into a 1-megabyte space. The 16-bit
space is divided into four separate zones. Each zone, except the first or root zone, has a
segment register that is added to the 16-bit address within the zone to create a 20-bit
address. The segment register has eight bits and those eight bits are added to the upper
four bits of the 16-bit address, creating a 20-bit address. Thus, each separate zone in the
16-bit memory becomes a window to a segment of memory in the 20-bit address space.
The relative size of the four segments in the 16-bit space is controlled by the SEGSIZE
register. This is an 8-bit register that contains two 4-bit registers. This controls the bound-
ary between the first and the second segment and the boundary between the second and
the third segment. The location of the two movable segment boundaries is determined by a
4-bit value that specifies the upper four bits of the address where the boundary is located.
These relationships are illustrated in Figure 3-3.
Memory
Chips
Processor
Memory
Mapping
Unit Memory
Interface
16
bits 20
bits
20 bits plus control