Slave port read cycle slave port write cycle, Scs sd[7:0] /srd, Swr sa1, sa0 – Jameco Electronics Rabbit 3000 User Manual

Page 209: Scs sd[7:0] /srd /swr sa1, sa0

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Rabbit 3000 Microprocessor

A status register can be read by either the slave or the master. The status register has full/
empty bits for each of the six registers. A data register is considered full when it is written
to by whichever side is capable of writing to it. If the same register is then read by either
side it is considered to be empty. The flag for that register is thus set to a "1" when the reg-
ister is written to, and the flag is set to a "0" when the register is read.

The registers appear to be internal I/O registers to the slave. To the master, at least for a
Rabbit master, the registers appear to be external I/O registers. The figure below shows the
sequence of events when the master reads/writes the slave port registers.

Figure 13-2. Slave Port R/W Sequencing

/SCS

SD[7:0]

/SRD

Slave Port Read Cycle

Slave Port Write Cycle

/SWR

SA1, SA0

Tsu(SCS)

Tsu(SA)

Th(SA)

Th(SCS)

Tw(SRD)

Ten(SRD)

Tdis(SRD)

Ta(SRD)

Tsu(SWR – SRD)

/SCS

SD[7:0]

/SRD

/SWR

SA1, SA0

Tsu(SCS)

Tsu(SA)

Th(SA)

Th(SCS)

Tw(SWR)

Th(SD)

Tsu(SD)

Tsu(SRD – SWR)

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