Jameco Electronics Rabbit 3000 - Manual (Page 53)

44 Rabbit 3000 Microprocessor
3.5 Interrupt Structure
When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con-
trol is transferred to the address of the interrupt service routine. The address of the inter-
rupt service routine has two parts: the upper byte of the address comes from a special
register and the lower byte is fixed by hardware for each interrupt, as shown in Table 6-1.
There are separate registers for internal interrupts (IIR) and external interrupts (EIR) to
specify the high byte of the interrupt service routine address. These registers are accessed
by special instructions.
LD A,IIR
LD IIR,A
LD A,EIR
LD EIR,A
Interrupts are initiated by hardware devices or by certain 1-byte instructions called reset
instructions.
RST 10
RST 18
RST 20
RST 28
RST 38
The RST instructions are similar to those on the Z80 and Z180, but certain ones have been
removed from the instruction set (00, 08, 30). The RST interrupts are not inhibited regard-
less of the processor priority. The user is advised to exercise caution when using these
instructions as they are mostly reserved for the use of Dynamic C for debugging. Unlike
the Z80 or Z180, the IIR register contributes the upper byte of the service routine address
for RST interrupts.
Since interrupt routines do not affect the XPC, interrupt routines must be located in the
root code space. However, they can jump to the extended code space after saving the XPC
on the stack.
3.5.1 Interrupt Priority
The Z80 and Z180 have two levels of interrupt priority: maskable and nonmaskable. The
nonmaskable interrupt cannot be disabled and has a fixed interrupt service routine address
of 0x66. The Rabbit, in contrast, has three levels of interrupt priority and four priority lev-
els at which the processor can operate. If an interrupt is requested, and the priority of the
interrupt is higher than that of the processor, the interrupt will take place after the execu-
tion of the current instruction is complete (except for privileged instructions)
Multiple interrupt priorities have been established to make it feasible for the embedded
systems programmer to have extremely fast interrupts available. Interrupt latency refers to
the time required for an interrupt to take place after it has been requested. Generally, inter-
rupts of the same priority are disabled when an interrupt service routine is entered. Some-
times interrupts must stay disabled until the interrupt service routine is completed, other
times the interrupts can be re-enabled once the interrupt service routine has at least dis-
abled its own cause of interrupt. In any case, if several interrupt routines are operating at