SUPER MICRO Computer SUPER X8STE - Manual (Page 77)

Chapter 4: AMI BIOS
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L0s is intended as a power saving state. It allows a link to quickly enter and
recover form a power saving state without going through recovery.
L1 is a power saving state that allows an additional power saving over L0s,
but with additional resume (wake-up) latency.
Select Enabled to activate QPI power saving (L0s and L1 are automatically
selected by the motherboard), select Disabled for normal operational state
without any power-saving function. The options are Disabled and
Enabled.
Memory Frequency
Use this option to force the system memory to run at a different frequency
than the default frequency. The available options are
Auto, Force DDR-800,
Force DDR-1066, and Force DDR-1333.
Memory Mode
The options are
Independent, Channel Mirror, Lockstep and Sparing.
Independent - All DIMMs are available to the operating system.
Channel Mirror - The motherboard maintains two identical copies of all data
in memory for redundancy.
Lockstep - The motherboard uses two areas of memory to run the same set
of operations in parallel.
Sparing - Memory sparing occurs when on-demand inactive memory is au-
tomatically activated by the system to temporarily replace failed memory until
a service action can be performed (supported only on 2010 Intel® Core™
processor family based on the 32nm Intel® microarchitecture).
Demand Scrubbing
Demand Scrubbing is a process that allows the CPU to correct correctable
memory errors found on a memory module. When the CPU or I/O issues a
demand-read command, and the read data from memory turns out to be a
correctable error, the error is corrected and sent to the requestor (the original
source). Memory is updated as well. Select Enabled to use Demand Scrub-
bing for ECC memory correction. The options are Enabled and
Disabled.
Patrol Scrubbing
Patrol Scrubbing is a process that allows the CPU to correct correctable
memory errors detected on a memory module and send the correction to the
requestor (the original source). When this item is set to Enabled, the North
Bridge will read and write back one cache line every 16K cycles, if there is
no delay caused by internal processing. By using this method, roughly 64 GB
of memory behind the North Bridge will be scrubbed every day. The options
are Enabled and
Disabled.