SMC Networks SMC91C95 - Manual (Page 10)

10
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
81 nByte High
Enable nSBHE I with pullup ISA - Byte High Enable input. Asserted (low)
by the system to indicate a data transfer on
the upper data byte.
nCard
Enable 2 nCE2 PCMCIA - Card Enable 2 input. Used to
select card on odd byte accesses.
83 Ready IOCHRDY OD24 with
pullup
ISA - Output. Optionally used by the
SMC91C95 to extend host cycles.
nWait nWAIT PCMCIA - Output. Optionally used by the
SMC91C95 to extend host cycles.
59, 60,
61, 63,
65, 66,
68-70,
72-74,
76-79
Data Bus D0-D15 I/O24 Bidirectional. 16 bit data bus used to access
the SMC91C95 internal registers. The data
bus has weak internal pullups. Supports direct
connection to the system bus without external
buffering.
98 Reset RESET IS with
pullup
Input. Active high Reset. This input is not
considered active unless it is active for at least
100ns to filter narrow glitches. A POR circuit
generates an internal reset upon power up for
at least 15msec. All hardware reset
references in this spec relate to the OR
function of the POR and the RESET pin.
82 Address
Latch BALE IS with
pullup
ISA - Input. Address strobe. For systems that
require address latching, the falling edge of
BALE latches address lines and nSBHE.
nWrite
Enable nWE PCMCIA - Write Enable input. Used for
writing into COR and CSR registers as well as
attribute memory space.
90 Interrupt INTR0 O24 ISA - Active high interrupt signal. The interrupt
line selection is determined by the value of
INT SEL1-0 bits in the Configuration Register.
This interrupt is tri-stated when not selected.