26
FIGURE 5 - TRANSMIT QUEUES AND MAPPING
B
A
B
C
STATUS
COUNT
DATA
STATUS
COUNT
DATA
PACKET #A
PACKET #B
PACKET NUMBER
REGISTER
TX FIFO
TO
CSMA
LINEAR ADDRESS
MMU MAPPING
MEMORY
CPU
SIDE
STATUS
COUNT
DATA
PACKET #C
TX COMPLETION
FIFO
FIFO PORTS
REGISTER
C