SMC Networks SMC91C95 - Manual (Page 87)

87
8024h - Pin Replacement Register (PRR)
7 6 5 4 3 2 1 0
Cready/-
Bsy
Rready/-
Bsy
0 0 0 0 0 0 1 0
Cready/-Bsy: This bit is set to a one when the
bit Rready/-Bsy bit changes state from zero(0)
to one(1) or one(1) to zero(0) with the source of
the change of state is a change in the modem
ready (MRDY) signal. The Cready/-Bsy bit can
be written by the CPU also. The CPU attempt
to write to this bit is masked by the value for Rready/Bsy bit. A CPU write to this
bit is successful only if the Rready/-Bsy bit is
being written as one(1). Note that the h/w
represented value of the Rready/-Bsy bit itself is
not affected by the write attempt as shown in
the following illustration:
CURRENT VALUE VALUE WRITTEN NEW VALUE
Cready/-Bsy Rready/-Bsy Cready/-Bsy Rready/-Bsy Cready/-Bsy Rready/Bsy
0 0 1 0 0 0
X 0 1 1 1 0
X 0 0 1 0 0
X 1 1 1 1 1
In the unlikely event that the MRDY changes
state at the same time that the nWE signal
changes from low to high (ie. writing the
register), the value written by the host will have
priority over the new state of the MRDY input
pin. Rready/-Bsy: When read, this bit represents
the current state of the modem Ready/-Busy
(MRDY) signal. Attempts of CPU writes to this
bit are ignored.