Index, Numbers, Index-1 – National Instruments SCXI-1163 User Manual

Page 97

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Index-1

SCXI-1163 User Manual

Index

Numbers

+5 V signal, 3-3, C-3

A

Address Handler

description, 4-2
register addresses, 4-2
selecting Data Register, 3-6
timing diagram, 2-21
writing to Address Handler, 2-21, 5-3

analog backplane protection, 3-7
AT-MIO board connection. See DIO-96,

AT-MIO-16D, and AT-MIO-64F-5
board connection.

B

backplane protection, 3-7

C

cabling

custom cables, optional, 1-3 to 1-4
DIO-96, AT-MIO-16D, and

AT-MIO-64F-5 board connection

SCXI-1163 and board pinout

equivalences, E-8 to E-9

SCXI-1351 and NB5 cable

assembly, E-7

SCXI-1351 and NB5 installation,

E-9 to E-10

multiple-chassis connections,

E-16 to E-17

SCXI-1180 feedthrough panel

cable assembly, E-12
installation, E-12 to E-13

SCXI-1302 50-pin terminal block

cover removal, E-15
installation, E-15
wiring procedure, E-14

SCXI-1340 cable assembly, E-1 to E-2

installation, E-3
SCXI-1163 and board pinout

equivalences, E-2

SCXI-1341 Lab-NB, Lab-PC, or

Lab-PC+ cable assembly, E-4

installation, E-5
pin translations, E-4

SCXI-1342 PC-LPM-16 cable

assembly, E-5

installation, E-6
pin translations, E-6

SCXI-1343 rear screw terminal adapter

cable assembly, E-17
installation, E-18
pin connections, E-17 to E-18

SCXI-1344 Lab-LC cable assembly, E-4

installation, E-5
pin translations, E-4

SCXI-1348 DIO-32F cable

assembly, E-10

installation, E-12
pin translations, E-11

SCXI-1350 multichassis adapter,

E-16 to E-17

SCXI-1351 one-slot cable extender

cable assembly, E-15
installation, E-16

channels. See output channels.
CHS<4..0> bit, Slot-Select Register, 4-8
CHSGND signal, SCXIbus connector,

3-3, C-3

communication signals, 2-19 to 2-24

Address Handler timing diagram, 2-21
communicating on SPI bus, 2-19
Data Register write timing diagram, 2-22
Module ID Register timing

diagram, 2-23

reading from Module ID Register, 2-23
reading from Status Register, 2-24
selecting a slot, 2-19
serial data timing diagram, 2-20
slot-select timing diagram, 2-19
SPI protocol, 2-3
Status Register timing diagram, 2-24
writing the slot-select number, 2-20
writing to Address Handler, 2-21

configuration. See jumper configuration;

module configuration;
signal connections.

custom cables, optional, 1-3 to 1-4
customer communication, xii, F-1

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