Chapter 1 introduction, About the reconfigurable i/o devices, About the reconfigurable i/o devices -1 – National Instruments NI PXI-7831R User Manual
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Introduction
This chapter describes the NI PXI-7831R, describes the concept of the
Reconfigurable I/O (RIO) device, lists what you need to get started,
describes the optional software and optional equipment, explains how
to unpack the hardware, and contains safety information about the
NI PXI-7831R.
About the Reconfigurable I/O Devices
Thank you for purchasing the NI PXI-7831R. This RIO device has 96
digital I/O (DIO) lines, 8 independent, 16-bit analog output (AO) channels,
and 8 independent, 16-bit analog input (AI) channels.
A user-reconfigurable field-programmable gate array (FPGA) controls the
digital and analog I/O on the NI PXI-7831R. The FPGA on the RIO device
allows you to define the functionality and timing of the device, whereas
traditional multifunction I/O (MIO) devices have a fixed functionality
provided by an application-specific integrated circuit (ASIC). You can
change the functionality of the FPGA on the RIO device by using
LabVIEW, a graphical programming environment, and the LabVIEW
FPGA Module to create and download a custom virtual instrument (VI) to
the FPGA. You can reconfigure the RIO device with a new VI at any time.
Using LabVIEW, you can graphically design the timing and functionality
of the RIO device without having to learn the low-level programming
language or hardware description language (HDL) that is traditionally used
for FPGA design. If you only have LabVIEW and do not have the FPGA
Module, you cannot create new FPGA VIs but you can create VIs that run
in LabVIEW to control existing FPGA VIs.
Some applications require tasks such as real-time, floating-point
processing or data logging while performing I/O and logic on the RIO
device. You can use the LabVIEW Real-Time (RT) Module to perform
these additional applications while also communicating with and
controlling the RIO device.
The RIO device contains flash memory to store VIs for instant loading of
the FPGA when the system is powered on.