National Instruments Eight-slot USB Chassis NI cDAQ-9172 - Manual (Page 26)

NI cDAQ-9172 User Guide and Specifications 26 ni.com
ActiveDevs and AI Convert Clock Rate properties using the DAQmx
Timing property node or functions.
Simultaneous Sample-and-Hold
Simultaneous sample-and-hold (SSH) C Series analog input modules
contain multiple A/D converters or circuitry that allows all the input
channels to be sampled at the same time. These modules sample their
inputs on every Sample Clock pulse.
Sigma-Delta
Sigma-delta C Series analog input modules function much like SSH
modules, but use A/D converters that require a high-frequency oversample
clock to produce accurate, synchronized data. Sigma-delta modules in
the cDAQ chassis automatically share a single oversample clock to
synchronize data from all sigma-delta modules.
This clock is used as the AI Sample Clock Timebase. While most modules
supply a common oversample clock frequency (12.8 MHz), some modules,
such as the NI 9234, supply a different frequency. When sigma-delta
modules with different oversample clock frequencies are used in an analog
input task, the AI Sample Clock Timebase can use any of the available
frequencies; by default, the fastest available is used. The sampling
rate of all modules in the system is an integer divisor of the frequency
of the AI Sample Clock Timebase.
When one or more sigma-delta modules are in an analog input task, the
sigma-delta modules also provide the signal used as the AI Sample Clock.
This signal is used to cause A/D conversion for other modules in the
system, just as the AI Sample Clock does when a sigma-delta module is not
being used.
When sigma-delta modules are in an AI task, the chassis automatically
issues a synchronization pulse to each sigma-delta modules that resets their
ADCs at the same time. Both the synchronization pulse and the oversample
clock can be routed from or to any PFI line to allow synchronization
between multiple chassis. Because of the filtering used in sigma-delta A/D
converters, these modules usually exhibit a fixed input delay relative to
non-sigma-delta modules in the system. This input delay is specified in the
C Series I/O module documentation.