National Instruments 6508 PCI-DIO-96 - Manual (Page 35)

Chapter 4 Theory of Operation
© National Instruments Corporation 4-3 PCI-DIO-96 User Manual
82C55A Programmable Peripheral Interface
The four 82C55A PPI chips are the heart of the PCI-DIO-96. Each of
these chips has 24 programmable I/O pins that represent three 8-bit
ports: PA, PB, and PC. Each port can be programmed as an input or
output port. The 82C55A has three modes of operation: simple I/O
(mode 0), strobed I/O (mode 1), and bidirectional I/O (mode 2). In
modes 1 and 2, the three ports are divided into two groups: group A and
group B. Each group has eight data bits and four control and status bits
from port C (PC). Modes 1 and 2 use handshaking signals from the
computer to synchronize data transfers. Refer to Chapter 6,
Programming, or to Appendix B, MSM82C55A Data Sheet, for more
detailed information.
82C53 Programmable Interval Timer
The 82C53 programmable interval timer generates timed interrupt
requests to your computer. The 82C53 has three 16-bit counters, which
can each be used in one of six different modes. The PCI-DIO-96 uses
two of the counters to generate interrupt requests; the third counter is
not used and is not accessible. Refer to Chapter 5, Register Map and
Description, or to Appendix C, MSM82C53 Data Sheet, for more
detailed information.
Interrupt Control Circuitry
Two software-controlled registers determine which devices, if any,
generate interrupts. Each of the four 82C55A devices has two interrupt
lines, PC3 and PC0, connected to the interrupt circuitry. The 82C53
device has two of its three counter outputs connected to the interrupt
circuitry. Any of these 10 signals can interrupt the computer if the
interrupt circuitry is enabled and the corresponding enable bit is set. See
Chapter 5, Register Map and Description, for more information.
Normally, the handshaking circuitry controls PC3 and/or PC0 of the
82C55A devices; however, you can configure either of these two lines
for input and then use them as external interrupts. An interrupt occurs
on the signal line low-to-high transition.
Refer to Chapter 5, Register Map and Description, Chapter 6,
Programming, Appendix B, MSM82C55A Data Sheet, or Appendix C,
MSM82C53 Data Sheet, for more detailed information concerning
interrupts.