National Instruments 6508 PCI-DIO-96 - Manual (Page 42)

Chapter 5 Register Map and Description
PCI-DIO-96 User Manual 5-6 © National Instruments Corporation
Figure 5-2. Control Word Format for the 82C53
Register Description for the Interrupt Control Registers
There are two interrupt control registers on the PCI-DIO-96. One of
these registers has individual enable bits for the two interrupt lines from
each of the 82C55A devices. The other register has a master interrupt
enable bit and two bits for the timed interrupt circuitry. Of the latter two
bits, one bit enables counter interrupts, while the other selects counter 0
or counter 1. The bit maps and signal definitions are listed in this
chapter.
D7 D6 D5 D4 D3 D2 D1 D0
Counter Select
00 = Counter 0
01 = Counter 1
10 = Counter 2
11 = Illegal
Access Mode
00 = Latch counter value
01 = Access LSB only
10 = Access MSB only
11 = Access LSB, then MSB
BCD
1 = Count in BCD
0 = Count in Binary
Mode Select
000 = Mode 0
001 = Mode 1
010 = Mode 2
011 = Mode 3
100 = Mode 4
101 = Mode 5
110 = Mode 2
111 = Mode 3