Gpctr0_source signal, Figure 4-27. gpctr0_source signal timing, Gpctr0_gate signal – National Instruments NI PCI-6110 User Manual

Page 61: Gpctr0_source signal -31 gpctr0_gate signal -31

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Chapter 4

Connecting Signals

© National Instruments Corporation

4-31

NI PCI-6110/6111 User Manual

GPCTR0_SOURCE Signal

Any PFI pin can externally input the GPCTR0_SOURCE signal, which is
available as an output on the PFI8/GPCTR0_SOURCE pin.

As an input, GPCTR0_SOURCE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR0_SOURCE and
configure the polarity selection for either rising or falling edge.

As an output, GPCTR0_SOURCE reflects the actual clock connected to
general-purpose counter 0, even if another PFI is externally inputting the
source clock. This output is set to high-impedance at startup.

Figure 4-27 shows the timing requirements for GPCTR0_SOURCE.

Figure 4-27. GPCTR0_SOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 10 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the
GPCTR0_SOURCE signal unless you select some external source.

GPCTR0_GATE Signal

Any PFI pin can externally input the GPCTR0_GATE signal, which is
available as an output on the PFI9/GPCTR0_GATE pin.

As an input, GPCTR0_GATE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR0_GATE and configure
the polarity selection for either rising or falling edge. You can use the gate
signal in a variety of different applications to perform actions such as
starting and stopping the counter, generating interrupts, and saving the
counter contents.

t

w

= 10 ns minimum

t

p

= 50 ns minimum

t

p

t

w

t

w

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