VXI VT1433B - Manual (Page 48)

All modules except the “system module” need to be set to use the VXI TTL
trigger lines as the clock source. Use hpe1432_setClockSource for this.
Set the “system module” to output the clock. Use hpe1432_setClockMaster for
this. After this is done, all system sync pulses come from the “system module”
and drive the measurement state machines on all boards in the group.
Possible Trigger Line Conflict
The following describes a scenario where VT1433B modules might conflict and
prevent a proper measurement. The conditions allowing the conflict are complex
but must be understood by the user.
After a measurement has completed, the modules are left set up. If a module
(call it module ‘A’) is driving the TTL trigger lines and a different group is
started which also drives the TTL trigger lines (and that different group does not
include module ‘A’), then module ‘A’ will conflict and prevent the other group
from functioning. In this case make a call to hpe1432_finishMeasure (using the
old group ID which includes ‘A’) to turn off module ‘A’ and allow the new
group to function.
Note that if the new group includes all modules of the old group, the conflict will
not occur since hpe1432_initMeasure will reset all modules as needed. Also note
that single-module groups do not drive the TTL trigger lines, so single-module
groups are immune from causing or receiving this conflict.
VT1433B User's Guide
Using the VT1433B
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