VXI VT1433B - Manual (Page 50)

In the example above, Mainframe A contains the Slot 0 Controller for a multiple
mainframe system. Mainframe A is connected to Mainframe B with a VXI-MXI
interface, Agilent/HP E1482B. To successfully manage this multiple mainframe
environment, use the following guidelines.
q Locate modules with logical addresses less than 128 in Mainframe A.
q Locate modules with logical addresses greater than 127 in Mainframe B.
q Locate the highest-numbered channels in Mainframe A.
q Locate the last module in the module list specified in the call to hpe1432_init in
Mainframe A.
q Locate the module that generates the group synchronization pulse in Mainframe A.
q Locate the channels performing channel triggering in Mainframe A.
q Locate the module with the shared sample clock in Mainframe A.
q If a groupID is not used with the call hpe1432_readRawData or
hpe1432_readFloat64Data, empty the VT1433Bs’ FIFOs in Mainframe B before
Mainframe A. In other words, do not empty the FIFOs in Mainframe A unless the
FIFOs in Mainframe B have been emptied. For more information about groupID
see “Grouping of Channels/Modules” in this chapter.
q If more than two mainframes are needed, daisy-chain them together. Treat each
mainframe after the first as a Mainframe B. See the example on the next page.
Phase Performance in Multiple Mainframe Measurements
Phase specifications are degraded by the delay that the inter-mainframe interface
gives the sample clock. This delay is insignificant for many low-frequency
applications because the phase error is proportional to frequency. A system with
two VXI-MXI modules and a one-meter cable, typically has a 76 nanosecond (ns)
sample clock delay in Mainframe B. This corresponds to an additional
0.007 degree phase error at 256 Hz and an additional 0.55 degree phase error at
20 kHz.
Using a four-meter cable (which adds approximately 18 ns of delay) causes a
total of 94 ns clock delay in Mainframe B. This corresponds to an additional
0.0087 degree phase error at 256 Hz and an additional 0.68 degree phase error at
20 kHz.
The cable adds approximately 6 ns per meter of cable.
Each daisy-chained mainframe adds another increment of delay, but only for the
additional cabling length.
VT1433B User's Guide
Using the VT1433B
3-12