Xilinx ML605 - Manual (Page 12)

12 www.xilinx.com ML605 Hardware User Guide
UG534 (v1.8) October 2, 2012
Chapter 1: ML605 Evaluation Board
Block Diagram
Figure 1-1 shows a high-level block diagram of the ML605 and its peripherals.
Related Xilinx Documents
Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources.
See
Appendix A, References for a direct link to Xilinx documentation. See the following
locations for additional documentation on Xilinx tools and solutions:
• ISE: www.xilinx.com/ise
• EDK: www.xilinx.com/edk
• Intellectual Property: www.xilinx.com/ipcenter
• Answer Browser: www.xilinx.com/support
X-Ref Target - Figure 1-1
Figure 1-1: ML605 High-Level Block Diagram
JTAG USB Mini-B
USB JTAG Circuit VITA 57.1 FMC
HPC Connector
VITA 57.1 FMC
LPC Connector
Virtex-6
FPGA
XC6VLX240T - 1FFG1156
System ACE CF
S.A. CompactFlash
S.A. 8-bit MPU I/F
User LED/SW
User DIP SW
User LCD
200 MHz LVDS Clock
SMA Clock
User S.E. 2.5V Clock
USB Controller
Host Type “A”
Peripheral Mini-B
Connectors
CP2103 USB-TO-UART
Bridge
USB Mini-B
Platform Flash
Linear BPI Flash
DVI Codec
VGA Video
DVI Video Connector
10/100/1000
Ethernet PHY
MII/GMII/RMII
SYSMON I/F
INIT, DONE LEDs
PROG PB, MODE SW
IIC Bus
IIC EEPROM
FMC HPC
DDR3 SODIMM IIC
FMC LPC
SFP Module
Connector
SGMII
PCIe X8 Edge Connector
MGT SMA REF Clock
MGT RX/TX SMA Port
UG534_01_092709
SODIMM Socket
204-pin, DDR3
Decoupling Caps
MEM Vterm
Regulator
BANK32 BANK12, 13
BANK14,22
BANK23,24
BANK112,113
BANK24
BANK34
BANK32
BANK33 BANK116
BANK33
BANK34
BANK15,16
BANK34,116
BANK0
BANK24,34 BANK14
BANK114
BANK115
BANK24 BANK14, 33, 36
BANK 25, 35
BANK 26, 36