Xilinx ML605 - Manual (Page 7)

ML605 Hardware User Guide www.xilinx.com 7
UG534 (v1.8) October 2, 2012
Preface
About This Guide
This manual accompanies the Virtex®-6 FPGA ML605 Evaluation Board and contains
information about the ML605 hardware and software tools.
Guide Contents
This manual contains the following chapters:
• Chapter 1, ML605 Evaluation Board , provides an overview of the embedded
development board and details the components and features of the ML605 board.
• Appendix B, Default Switch and Jumper Settings .
• Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout .
• Appendix D, ML605 Master UCF .
• Appendix A, References .
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/support/documentation/virtex-6.htm .
• Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
• Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Virtex-6 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
• Virtex-6 FPGA Clocking Resources User Guide
This guide describes the clocking resources available in all Virtex-6 devices, including
the MMCM and PLLs.