Xilinx ML605 - Manual (Page 14)

14 www.xilinx.com ML605 Hardware User Guide
UG534 (v1.8) October 2, 2012
Chapter 1: ML605 Evaluation Board
7
Clock generation
200 MHz OSC, oscillator socket, SMA
connectors
30
a. 200 MHz oscillator (on
backside)
SiTime 200 MHz 2.5V LVDS OSC 30
b. Oscillator socket, single-
ended
MMD Components 66 MHz 2.5V 30
c. SMA connectors SMA pair 30
d. MGT REFCLK SMA
connectors
SMA pair 30
8 GTX RX/TX port SMA x4 30
9
PCIe Gen1 (8-lane),
Gen2 (4-lane)
Card edge connector, 8-lane 21
10 SFP connector and cage AMP 136073-1 23
11
Ethernet (10/100/1000) with
SGMII
Marvell M88E1111 EPHY 24
12
USB Mini-B, USB-to-UART
bridge
Silicon Labs CP2103GM bridge 33
13
USB-A Host, USB Mini-B
peripheral connectors Cypress CY7C67300-100AXI
controller
27
14 Video - DVI connector Chrontel CH7301C-TF Video codec 28, 29
15
IIC NV EEPROM, 8 Kb
(on backside) ST Microelectronics M24C08-
WDW6TP
32
16
Status LEDs 13, 24, 31
a. Ethernet status Right-angle link rate and direction
LEDs
24
b. FPGA INIT, DONE Init (red), Done (green) 31
c. System ACE CF status Status (green), Error (red) 13
17
User I/O 31
a. User LEDs, green (8) User I/O (active-High) 30, 31, 33
b. User pushbuttons, N.O.
momentary (5)
User I/O (active-High) 31
c. User LEDs, green (5) User I/O (active-High) 31
d. User DIP switch (8-pole) User I/O (active-High) 31
e. User GPIO SMA
connectors
SMA pair 30
f. LCD 16 character x 2 line
display
Displaytech S162D BA BC 33
Table 1-1: ML605 Features (Cont’d)
Number Feature Notes
Schematic
Page