Rainbow Electronics ATmega8HVD - Manual (Page 101)

101
8052B–AVR–09/08
ATmega4HVD/8HVD
19.3 Battery Pack Short mode
The Voltage Regulator has a separate Short-Circuit Detection mode (RSCD) that can be
enabled or disabled by SW. This mode should always be enabled except when operating at
VFET voltages below V
FORCE
(see TBD-electrical chara). The mode is intended for sustaining
operation during short spikes on VFET that can occur for instance during a battery pack inser-
tion. The mode is entered when VFET drops below V
FORCE
and Regulator Short-circuit
Detection is enabled. In the Battery Pack Short mode, VFET is temporarily disconnected from
VREG to avoid a quick drop in the voltage regulator output. The chip will be completely pow-
ered by the external reservoir capacitor (CREG). This allows the chip to operate a certain time
before entering BLOD reset (power-off) even if the VFET voltage is too low for the voltage reg-
ulator to operate.
The maximum time that the chip can operate in the Battery Pack Short mode is given by the
size of the external reservoir capacitor and the actual power drawn from VREG. The VREG
voltage must stay above V
BLOT,normal
to avoid that the chip enters power-off. If a battery pack
short occurs when VREG = 2.2V and V
BLOT, normal
is 2.0V the chip can operate for a time given
by:
where I
AVG
represents the average current drawn from CREG. For CREG = 2.2 µF and
I
AVG
= 100 µA, this time equals 4.4 ms. Refer to Table 19-2 on page 102 for an example of
Regulator Short-circuit Detection.
19.4 Regulator Force mode
The regulator Force mode is designed to be able to operate the chip even at very low cell volt-
ages. This mode is automatically entered when the VFET voltage drops below V
FORCE-
provided that the Regulator Short-circuit Detection is disabled. To ensure operation down to
minimum VFET level, Regulator Short-circuit Detection should always be disabled before
VFET reaches V
FORCE-
during discharge.
An example of VREG voltage as function of VFET when using the voltage regulator as
intended, is shown in figure 66. When VFET > V
FORCE
, VREG is regulated to 2.2V (nominal
value). When VFET approaches V
FORCE
, Regulator Short-circuit Detection is disabled, and
when VFET passes V
FORCE-
, the regulator enters FORCE mode. When this occurs, a disconti-
nuity in VREG can be observed. This is caused by the fact that VREG is no longer regulated
and is forced as close to VFET as possible. A small difference V
DROP
between VFET and
VREG can be observed. This voltage drop depends on the load current. Typical vales can be
found in TBD-El.Chara. The chip will continue operation in FORCE mode until VREG reaches
the BLOD level and the chip enters power-off.
When using VREG as reference for external measurements, for instance as reference for an
external thermistor as shown in TBD-operating circuit, it may be required to know the accurate
value of VREG. In FORCE mode, VREG will range from V
FORCE
to VFET
min
, as opposed to
normal regulation where VREG has a constant value. Since ATmega4/8HVD has no method
of measuring VREG directly, it is recommended to measure the cell voltage and estimate
VREG based on loss through Charge FET (if applied) and voltage drop from VFET to VREG
according to the following formula:
T
c
Δ
(v)
⋅
I
AVG
------------------
CREG 0.2V
⋅
I
AVG
--------------------------------- = =
VREG
FORCE
V
Cell
V
DS CFET –
– V
DROP
– =