Rainbow Electronics ATmega8HVD - Manual (Page 109)

109
8052B–AVR–09/08
ATmega4HVD/8HVD
• Bit 1 – BPPLE: Battery Protection Parameter Lock Enable
• Bit 0 – BPPL: Battery Protection Parameter Lock
The BPCR, BPOCTR, BPSCTR, BPDOCD, BPCOCD and BPSCD Battery Protection regis-
ters can be locked from any further software updates. Once locked, these registers cannot be
accessed until the next hardware reset. This provides a safe method for protecting the regis-
ters from unintentional modification by software runaway. It is recommended that software
sets these registers shortly after reset, and then protect the registers from further updates.
To lock these registers, the following algorithm must be followed:
1. In the same operation, write a logic one to BPPLE and BPPL.
2. Within the next four clock cycles, in the same operation, write a logic zero to BPPLE
and a logic one to BPPL.
20.8.2 BPCR – Battery Protection Control Register
• Bit 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• bit 5 – EPID: External Protection Input Disable
When this bit is set, the External Protection Input is disabled and any External Protection Input
will be ignored. Note that this bit overrides the GPIO functionallity in the External Protection
Input port. If not using the External Protection Input feature, it is recommended that this bit is
always set.
• Bit 4 – SCD: Short Circuit Protection Disable
When the SCD bit is set, the Short-circuit Protection is disabled. The Short-circuit Detection
will be disabled, and any Short-circuit condition will be ignored.
• Bit 3 – DOCD: Discharge Over-current Protection Disable
When the DOCD bit is set, the Discharge Over-current Protection is disabled. The Discharge
Over-current Detection will be disabled, and any Discharge Over-current condition will be
ignored.
• Bit 2 – COCD: Charge Over-current Protection Disable
When the COCD bit is set, the Charge Over-current Protection is disabled. The Charge Over-
current Detection will be disabled, and any Charge Over-current condition will be ignored.
• Bit 1:0 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCR register is written. Any
writing to the BPCR register during this period will be ignored.
Bit 7 6 5 4 3 2 1 0
– – EPID SCD DOCD COCD - - BPCR
Read/Write R R R/W R/W R/W R/W R R
Initial Value 0 0 0 0 0 0 0 0