Rainbow Electronics ATmega8HVD - Manual (Page 127)

127
8052B–AVR–09/08
ATmega4HVD/8HVD
23.6 Register Description
23.6.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to
control the Program memory operations.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bits must be
written to zero when SPMCSR is written.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. See
”Reading
the Signature Row from Software” on page 124 for details.
An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.
This operation is reserved for future use and should not be used.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will
be cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Regis-
ter, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See
”EEPROM Write Prevents Writing to SPMCSR” on page 123 for
details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is exe-
cuted within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of
a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted
during the entire Page Write operation.
• Bit 0 – SPMEN: Store Program Memory Enable
Bit 7 6 5 4 3 2 1 0
– – SIGRD CTPB RFLB PGWRT PGERS SPMEN SPMCSR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0