Rainbow Electronics ATmega8HVD - Manual (Page 118)

118
8052B–AVR–09/08
ATmega4HVD/8HVD
• Bit 1 – DFE: Discharge FET Enable
When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state
of the Battery Protection circuitry. When this bit is set (one), the Discharge FET is enabled.
This bit will automatically be cleared by the CBP circuitry when Current Protection is activated.
When this bit is cleared, Short-circuit, Discharge High-current and Discharge Over-current are
disabled regardless of the settings in the BPCR Register.
• Bit 0 – CFE: Charge FET Enable
When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Charge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared and the DUVRD bit is set, Charge High-current Protection and Charge Over-
current Protection are disabled regardless of the settings in the BPCR Register. When the
DUVRD bit is cleard, the charge FET will be enabled by DUVT mode regardless of the CFE
status.
Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the FCSR register is written. Any
writing to the FCSR register during this period will be ignored.