Rainbow Electronics ATmega8HVD - Manual (Page 71)

71
8052B–AVR–09/08
ATmega4HVD/8HVD
15. Timer/Counter0 and Timer/Counter1 Prescalers
15.1 Overview
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Coun-
ters can have different prescaler settings. The description below applies to both
Timer/Counter1 and Timer/Counter0.
15.2 Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
CLK_I/O
). Alternatively, one of four taps from the prescaler can be
used as a clock source. The prescaled clock has a frequency of either f
CLK_I/O
/8, f
CLK_I/O
/64,
f
CLK_I/O
/256, or f
CLK_I/O
/1024.
15.3 Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implica-
tions for situations where a prescaled clock is used. One example of prescaling artifacts
occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1
to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
Figure 15-1. Prescaler for Timer/Counter
PSRSYNC
Clear
clk
Tn
Tn
clk
I/O
Synchronization
CSn0
CSn1
CSn2
n