6 timskn – timer/counter n interrupt mask register, 7 tifrn – timer/counter n interrupt flag register, Atmega4hvd/8hvd – Rainbow Electronics ATmega8HVD User Manual
Page 88
88
8052B–AVR–09/08
ATmega4HVD/8HVD
In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Reg-
ister. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
Registers in 16-bit Mode” on page 82
16.10.6
TIMSKn – Timer/Counter n Interrupt Mask Register
• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector (
) is executed when the ICFn flag, located in TIFRn, is
set.
• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter occurs, i.e., when the OCFnB bit is set in the
Timer/Counter Interrupt Flag Register – TIFRn.
• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a Compare Match in Timer/Counter n occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter n occurs, i.e., when the TOVn bit is set in the Timer/Counter n Inter-
rupt Flag Register – TIFRn.
16.10.7
TIFRn – Timer/Counter n Interrupt Flag Register
• Bits 3 – ICFn: Timer/Counter n Input Capture Flag
This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and
ICSn bits in the TCCRnA Register.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alterna-
tively, ICFn can be cleared by writing a logic one to its bit location.
Bit
7
6
5
4
3
2
1
0
-
-
-
-
ICIEn
OCIEnB
OCIEnA
TOIEn
TIMSKn
Read/Write
R
R
R
R
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
-
-
-
-
ICFn
OCFnB
OCFnA
TOVn
TIFRn
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0