Teledyne LeCroy TA700_800_850 User Manual - Manual (Page 249)

APPENDIX C Catalyst Enterprises, Inc.
235
Bus Protocol & Speed Sensing
Note: The JP10 jumper settings tell the central system arbiter the capability of the board.
The PCI and PCI-X bus speed and type is determined by the system BIOS at
powerup. During the time that RST# is asserted, the system reads the signals on D21
(M66EN) and B16 (PCIX CAP) from all of the boards asserted on the bus. At the
rising edge of RST# a message defining the bus protocol and operating speed that
satisfies the lowest performance on the bus is sent to all of the cards on the bus. This
message is sent by the following five control signals: FRAME, IRDY#, TRDY#,
DEVSEL# and STOP#.
Caution The JP10 setting information and the bus data returned at the rising edge of RST#
do not have to match if there is more than one agent on the bus.
JP10
Shunt 1-2 Top two PCI-X 133MHz
Shunt 3-4 Next to top N/A
Shunt 5-6 Next to bottom PCI-X 66MHz
Shunt 7-8 Bottom two PCI (Default)