IEI Integration PICOe-HM650 - Manual (Page 44)

PICOe-HM650 Half-size PCIe CPU Card
Page 30
Figure 3-15: LVDS Connector Location
Pin Description Pin Description
1 GND 2 GND
3 A_Y0 4 A_Y0#
5 A_Y1 6 A_Y1#
7 A_Y2 8 A_Y2#
9 A_CK 10 A_CK#
11 A_Y3 12 A_Y3#
13 GND 14 GND
15 B_Y0 16 B_Y0#
17 B_Y1 18 B_Y1#
19 B_Y2 20 B_Y2#
21 B_CK 22 B_CK#
23 B_Y3 24 B_Y3#
25 GND 26 GND
27 VCC/VCC3 28 VCC/VCC3
29 VCC/VCC3 30 VCC/VCC3
Table 3-16: LVDS Connector Pinouts