Cirrus Logic CS4244 - Manual (Page 27)

DS900F1 27
CS4244
4.4.2 Master Mode Clock Ratios
As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK
is equal to F
S
and SCLK is equal to 64x F
S
as shown in Figure 13 . TDM format is not supported in Master
Mode.
The resulting valid master mode clock ratios are shown in Table 3 below.
4.4.3 Slave Mode Clock Ratios
In Slave Mode, SCLK and FS/LRCK operate as inputs. The FS/LRCK clock frequency must be equal to
the sample rate, F
S
, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
512x, 256x, 128x, 64x, 48x or 32x F
S
, depending on the desired format and speed mode. Refer to Table 4
and Table 5 for required clock ratios.
Note:
34. For all cases, the SCLK frequency must be less than or equal to the MCLK frequency.
SSM DSM
MCLK/F
S
256x, 384x, 512x 128x, 192x, 256x
SCLK/F
S
64x 64x
Table 3. Master Mode Left Justified and I²S Clock Ratios
SSM DSM
MCLK/F
S
256x, 384x, 512x 128x, 192x, 256x
SCLK/F
S
32x, 48x, 64x, 128x 32x, 48x, 64x
Table 4. Slave Mode Left Justified and I²S Clock Ratios
(Note 34) SSM DSM
MCLK/F
S
256x, 384x, 512x 512x 256x
SCLK/F
S
256x 512x 256x
Table 5. Slave Mode TDM Clock Ratios
ч512
ч256
ч8
ч4
00
01
00
01
FS/LRCK
SCLK
000
001
010
x2
ч1.5
ч1
MCLK Speed Mode Bits
MCLK Rate Bits
x2
PLL active
Figure 13. Master Mode Clocking