Cirrus Logic CS4244 - Manual (Page 56)

DS900F1 56
CS4244
6.16 Interrupt Mask 1 (Address 1Fh)
6.16.1 Test Mode Error Interrupt Mask
Controls whether a Test Mode Error event flags the interrupt pin. A test mode error occurs when an inad-
vertent I²C write places the device in test mode.
6.16.2 Serial Port Error Interrupt Mask
Controls whether the interrupt pin if flagged when any of the following parameters are changed without
first powering down the device (i.e., setting all
Power Down ADCx and Power Down DACx bits):
• Serial Port Format: SP FORMAT[1:0]
• Speed Mode: SPEED MODE (In slave mode, changing the MCLK/F
S
ratio without powering down the
device, flags this error and the Clocking Error. In master mode, changing MCLK frequency without the
device being powered down does not flag this or the Clocking Error since MCLK/F
S
does not change.)
• Master/Slave: MSTR/SLV
6.16.3 Clocking Error Interrupt Mask
Allows or prevents a Clocking Error event from flagging the interrupt pin. See Section 4.8 for details.
6.16.4 ADCx Overflow Interrupt Mask
Allows or prevents an ADCx Overflow event from flagging the interrupt pin.
7 6 5 4 3 2 1 0
MASK
TST MODE ERR
MASK
SP ERR
MASK CLK ERR Reserved
MASK
ADC4 OVFL
MASK
ADC3 OVFL
MASK
ADC2 OVFL
MASK
ADC1 OVFL
MASKTSTMOD ERR In the event of a Test Mode Error event, Interrupt Pin will:
0
Be Flagged
1 Not be flagged
MASK SP ERR In the event of a Serial Port Error event, Interrupt Pin will:
0 Be Flagged
1 Not be flagged
MASK CLK ERR In the event of a Clocking Error event, Interrupt Pin will:
0
Be Flagged
1 Not be flagged
MASK ADCx OVFL In the event of an ADCx Overflow event, Interrupt Pin will:
0
Be Flagged
1 Not be flagged