4 sample width select (address 07h), 1 output sample width, 2 input sample width – Cirrus Logic CS4244 User Manual
Page 49: 5 serial port control (address 08h), 1 invert sclk, 2 serial port format, Serial port format, Cs4244
DS900F1
49
CS4244
6.4
Sample Width Select (Address 07h)
6.4.1
Output Sample Width
These bits set the width of the samples placed into the outgoing SDOUTx streams.
Note:
Bits wider than the Output Sample Width setting are cleared within the SDOUTx data stream.
6.4.2
Input Sample Width
These bits set the width of the samples coming into the CS4244 through the SDINx TDM streams.
Note:
In Left Justified or I²S mode, the Input Sample Width is fixed to 24 bits.
6.5
Serial Port Control (Address 08h)
6.5.1
Invert SCLK
When set, this bit inverts the polarity of the SCLK signal.
6.5.2
Serial Port Format
Sets the format of both the incoming serial data signals and outgoing serial data signals.
7
6
5
4
3
2
1
0
SDOUTx SW[1:0]
INPUT SW[1:0]
Reserved[1:0]
Reserved[1:0]
OUTPUT SW
Sample Width is:
00
16 bits
01
18 bits
10
20 bits
11
24 bits
INPUT SW
Sample Width is:
00
16 bits
01
18 bits
10
20 bits
11
24 bits
7
6
5
4
3
2
1
0
INV SCLK
Reserved[2:0]
SP FORMAT[1:0]
SDO CHAIN
MASTER/
SLAVE
INV SCLK
SCLK is:
0
Not Inverted
1
Inverted
SP FORMAT
Format is:
00
Left Justified
01
I²S
10
TDM (Slave Mode Only)
11
Reserved