Table 10. adc digital interface formats, 3 mute adc (bit 2), 4 adc high-pass filter freeze (bit 1) – Cirrus Logic CS4265 User Manual

Page 39: 5 master / slave mode (bit 0), 5 mclk frequency - address 05h, 1 master clock dividers (bits 6:4), Table 11. mclk frequency, Bits (see, Mclk frequency - address 05h, Table 10

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Table 10. adc digital interface formats, 3 mute adc (bit 2), 4 adc high-pass filter freeze (bit 1) | 5 master / slave mode (bit 0), 5 mclk frequency - address 05h, 1 master clock dividers (bits 6:4), Table 11. mclk frequency, Bits (see, Mclk frequency - address 05h, Table 10 | Cirrus Logic CS4265 User Manual | Page 39 / 57 Table 10. adc digital interface formats, 3 mute adc (bit 2), 4 adc high-pass filter freeze (bit 1) | 5 master / slave mode (bit 0), 5 mclk frequency - address 05h, 1 master clock dividers (bits 6:4), Table 11. mclk frequency, Bits (see, Mclk frequency - address 05h, Table 10 | Cirrus Logic CS4265 User Manual | Page 39 / 57
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