Cirrus Logic CS4265 - Manual (Page 28)

28 DS657F3
CS4265
topology. If pseudo-differential input functionality is not required, simply connect the SGND pin to AGND
through the parallel combination of a 10 µF and a 0.1 µF capacitor.
4.6 Output Connections
The CS4265 DACs implement a switched-capacitor filter, followed by a continuous time low-pass filter. Its
response, combined with tha t of the digital interpolator, is sh own in Section 8. “DAC Filter Plots” on
page 48 ”. The recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4265 DAC does not include phase or amplitude compensation for an external filter. Therefore, the
DAC system phase and amplitude response is dependent on the external analog circuitry.
4.7 Output Transient Control
The CS4265 uses Popguard ® technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended, single-
supply converters when it is implemented with external DC-blocking capacitors connected in series with the
audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1 Power-Up
When the device is initially powered-up, the DAC outputs AOUTA and AOUTB are clamped to VQ, which
is initially low. After the PDN bit is released (set to ‘0’), the outputs begin to ramp with VQ towards the
nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the qui-
escent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2 Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this, either the PDN should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VQ and the DAC outputs will gradually
discharge to GND. If power is removed before this 250 ms time period has passed, a transient will occur
when the VA supply drops below that of VQ. There is no minimum time for a power cycle; power may be
re-applied at any time.
4.7.3 Serial Interface Clock Changes
When changing the clock ratio or sample rate, it is recommended that zero data (or near zero data) be
present on the selected SDIN pin for at least 10 LRCK samples before the change is made. During the
+
-
VA
+
-
AINA
AINB
SG ND
In to PG A
In to PG A
10 µF
0.1 µF
Note: If pseudo-differential input functionality is not required, the
connections shown with dashed line should be added.
Figure 12. Pseudo-Differential Input Stage
CS4265