1 accessing the e buffer, Figure 45. flowchart for writing the e buffer, 2 serial copy management system (scms) – Cirrus Logic CS4265 User Manual

Page 54: 3 channel status data e buffer access, Figure 45.flowchart for writing the e buffer, Cs4265

Advertising
background image

54

DS657F3

CS4265

11.1.1

Accessing the E Buffer

The user can monitor the data being transferred by reading the E buffer, which is mapped into the register

space of the CS4265, through the control port. The user can modify the data to be transmitted by writing

to the E buffer.

The E buffer is only accessible when an MCLK signal is applied to the CS4265 and the device is out of

the power-down state (the PDN bit in register 02h is cleared). If either of these conditions is not met, the

values stored in the E buffer will not change when written via the control port.

The user can configure the status register such that EFTC bit is set whenever an E to F transfer com-

pletes. With this configuration in place, periodic polling of the status register allows determination of the

time periods acceptable for E buffer interaction.

Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this

bit. This may be used whenever “long” control port interactions are occurring.

A flowchart for reading and writing to the E buffer is shown in

Figure 45

. For writing, the sequence starts

after an E to F transfer, which is based on the output time base.

11.2

Serial Copy Management System (SCMS)

The CS4265 allows read/modify/write access to all the channel status bits. For consumer mode SCMS com-

pliance, the host microcontroller needs to manipulate the Category Code, Copy bit and L bit appropriately.

11.3

Channel Status Data E Buffer Access

The E buffer is organized as 24 x 16-bit words. For each word, the most significant byte is the A channel

data, and the least significant byte is the B channel data (see

Figure 44

).

There are two methods of accessing this memory, known as One-Byte Mode and Two-Byte Mode. The de-

sired mode is selected through a control register bit.

Read the Status Register

(Reg 0Dh)

If set, clear E to F inhibit

Write E data

Optionally set E to F inhibit

Is the EFTC bit set?

Configure the EFTC status bit as

Rising Edge active.

Begin

Yes

No

Figure 45. Flowchart for Writing the E Buffer

Advertising