Cirrus Logic CS4265 - Manual (Page 33)

DS657F3 33
CS4265
4.15 Reset
When RESET is low, the CS4265 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET is high, the control port becomes operation-
al, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Pow-
er Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted.
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.16 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the master clocks a nd left/right clocks mu st be the same for all o f the
CS4265s in the system. If only one master clock source is needed, one solution is to place one CS4265 in
Master Mode, and slave all of the other CS4265s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS4265 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
4.17 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS4265 requires careful attention to power supply and grounding
arrangements if its po tential performance is to b e realized. Figure 9 shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this
case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as
near to the CS4265 as possible, with the low value ceramic capacitor being the nearest. All signals, espe-
cially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the
modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to mini-
mize the electrical path from FILT+ and AGND. The CS4265 evaluation board demonstrates the optimum
layout and power supply arrangements. To minimize digital noise, connect the CS4265 digital outputs only
to CMOS inputs.
4.18 Package Considerations
The CS4265 is available in the compact QFN package. The under side of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS4265 evaluation board demonstrates the optimum thermal pad and via configuration.