8 dac serial data input multiplexer, 9 de-emphasis filter, Figure 13. de-emphasis curve – Cirrus Logic CS4265 User Manual

Page 29: 10 internal digital loopback, Figure 13.de-emphasis curve, Cs4265

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DS657F3

29

CS4265

clocking change, the DAC outputs will always be in a zero-data state. If non-zero serial audio input is

present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes

to its zero-data state.

4.8

DAC Serial Data Input Multiplexer

The CS4265 contains a 2-to-1 serial data input multiplexer. This allows two separate data sources to be

input into the DAC without the use of any external multiplexing components.

Section 6.6.1 “DAC SDIN

Source (Bit 7)” on page 40

describes the control port settings necessary to control the multiplexer.

4.9

De-Emphasis Filter

The CS4265 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-

sponse is shown in

Figure 13

. The frequency response of the de-emphasis curve scales proportionally with

changes in sample rate, Fs. Please see

Section 6.3.3 “De-Emphasis Control (Bit 1)” on page 38

for de-em-

phasis control.

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis

equalization as a means of noise reduction.

De-emphasis is only available in Single-Speed Mode.

4.10

Internal Digital Loopback

The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input

of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See

“Signal

Selection - Address 06h” section on page 40

).

When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265.

Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until

the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the

format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin

in the format selected by the ADC_DIF bit in register 04h.

Gain

dB

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1

F2

3.183 kHz

10.61 kHz

Figure 13. De-Emphasis Curve

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