Cirrus Logic CS4265 - Manual (Page 25)

DS657F3 25
CS4265
In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK
ratio to achieve a post-divider MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM. Table 3
lists the appropriate dividers.
4.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 10 .
4.2.3 Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to Table 4 for required clock ra-
tios.
4.3 High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven
into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset
MCLK/LRCK Ratio MCLK Dividers
64x
- - ÷1
96x
- - ÷1.5
128x
- ч1 ч2
192x
- ч1.5 ч3
256x
ч1 ч2 ч4
384x
ч1.5 ч3 -
512x
ч2 ч4 -
768x
÷3 - -
1024x
÷4 - -
Mode SSM DSM QSM
Table 3. MCLK Dividers
Single-Speed Double-Speed Quad-Speed
SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x
Table 4. Slave Mode Serial Bit Clock Ratios
ч256
ч128
ч64
ч4
ч2
ч1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
ч1
ч1.5
ч2
011
100
ч3
ч4
MCLK FM Bits
MCLK Freq Bits
Figure 10. Master Mode Clocking