Cirrus Logic CS4265 - Manual (Page 40)

40 DS657F3
CS4265
6.6 Signal Selection - Address 06h
6.6.1 DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in Table 12 .
6.6.2 Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
“Internal Digital Loopback” on page 29 .
6.7 Channel B PGA Control - Address 07h
6.7.1 Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 40.
6.8 Channel A PGA Control - Address 08h
6.8.1 Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 13 for ex-
ample settings.
7 6 5 4 3 2 1 0
SDINSel Reserved Reserved Reserved Reserved Reserved LOOP Reserved
SDINSel Setting DAC Data Source
0 SDIN1
1 SDIN2
Table 12. DAC SDIN Source Selection
7 6 5 4 3 2 1 0
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
7 6 5 4 3 2 1 0
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
Gain[5:0] Setting
101000 -12 dB
000000 0 dB
011000 +12 dB
Table 13. Example Gain and Attenuation Settings